Figures 1-5: As found. The FSD bit shown in Figure 5 I thought would be tripped in the event that the Hall A ion chambers lose HV.
Chain of events in control room -- Figure 2, got alarms on Hall A ion chambers. Was delivering CW. Brought up Figure 1: Saw all HVs on Hall A ion chambers zero. Figure 5: FSD bit clear, not masked at a higher level, as shown in Figures 3 and 4. So no FSD fault as expected.
Turning on HV as we need these ion chambers.
HV came back up without issue.
Jim Coleman and I checked out the supply. Multiple attempts had the supply tripping off at approximately 11.5% of rated output, due to either a DC Overload or Phase Imbalance fault, or both (nothing consistent). Diagnostic signals looked terrible. We locked out the supply, examined the Transistor Bank and SCR assemblies. After removing our locks, we tried to turn on the supply, it took cycling the main input power 3 times to clear immediate DC Overload faults. We finally got the supply on, got it up to 50% of rated output and monitored its operation.
for reference. Operational restriction descriptions will soon be better matched to this. Searching for target ladder gets a March 2017 screen. This one doesn't show up in search with any string I tried. It is the last link in figure 2.